The Easy Steps to Calculate Sampling Clock Jitter for Isolated, Precision High-Speed DAQs

The Easy Steps to Calculate Sampling Clock Jitter for Isolated, Precision High-Speed DAQs

This article will explain how to interpret the jitter specifications on Analog Devices’ LVDS digital isolators and which specifications are important when interfacing to precision, high speed products such as the ADAQ23875 DAQ μModule® solution. The guidance outlined in this article is applicable when using other precision, high speed ADCs with an LVDS interface. The approach for calculating the expected impact on the SNR will also be explained in the context of the ADAQ23875 when used in conjunction with the ADN4654 gigabit LVDS isolator.