Optimizing for best power during place and route in low power SoC designs
Traditionally, when talking about performance, power, and area (PPA) metrics, “performance” has been a primary focus. But as designs have moved to smaller, more advanced…
Traditionally, when talking about performance, power, and area (PPA) metrics, “performance” has been a primary focus. But as designs have moved to smaller, more advanced…
Electronic systems of all sizes are routinely being integrated into single integrated circuits (ICs). While the largest systems-on-chip (SoC) make headlines, there are numerous small…
This white paper goes through the journey of understanding how to meet quality requirements and accelerate time-to-market for your company’s latest flagship high performance computing…
Electrical rule checking (ERC) is an important part of design verification for any integrated circuit (IC) or chip design. ERC verifies the robustness of a…
Automated post-processing DRC debugging flows enable designers to more quickly and accurately analyze and fix (or waive) a wide range of complex error conditions. By…
Ensuring your integrated circuit (IC) design has the ability to withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity….
Understanding the cost/benefit relationship of cloud computing helps companies determine the optimal configuration that provides the greatest returns. In this paper, see the results of…
The electronics used in aerospace applications need to stand up to the harsh environment outside of the earth’s protective atmosphere. As the European Space Agency…
The Aprisa digital design software helps designers address the many challenges of low-power designs. Aprisa is the most flexible IC place-and-route tool on the market—it…
Increased design complexity, protocols, embedded software, power and verification at the system level all drive the need for the kind of performance, capacity, and “shift-left” methodology that…