System-level connectivity management and verification of 3D IC heterogeneous assemblies

System-level connectivity management and verification of 3D IC heterogeneous assembliesCapturing the intended system-level connectivity in a multi-substrate 3D IC assembly can be a challenge. This is especially true when each substrate is built using a different methodology, team, and/or format.

 

This paper discusses the system level connectivity challenge, assembly verification challenges and a design-centric approach to dealing with these challenges.