Power structure design is becoming more challenging with every advance in technology nodes. Voltage drop (IR) and electromigration (EM) issues are growing in number and impact. Designers must find a way to manage increasing resistance from narrower metals, which has a direct effect on reliability and yield. With the increasing complexity of via rules required at advanced nodes, traditional custom scripts used to add vias have become too complex and time-consuming to control different stacks, complex spacing rules, different enclosure, and via count per width. The use of such scripts extends the time to market, impacting competitive positioning and profitability.
Download this paper to learn how the Calibre YieldEnhancer PowerVia utility uses manufacturing requirements to perform automated insertion of DRC/LVS-clean vias. Results show significant improvements in EM/IR results, including substantial reductions in current density violations.