Optimizing for best power during place and route in low power SoC designs

Optimizing for best power during place and route in low power SoC designsTraditionally, when talking about performance, power, and area (PPA) metrics, “performance” has been a primary focus. But as designs have moved to smaller, more advanced process nodes, and as switching activity has become a dominant component in power consumption, power consumption is growing in importance. 

 

How can strict power specs be achieved without sacrificing performance during the implementation phase of the IC design process? This eBook introduces tools and new methodologies to better manage this metric. By starting with the power metric as the top goal during optimization, the place-and-route flow can achieve the best possible power for that node, library, and design specs, and then optimize from that point to reach the timing target.