Deliver 3D IC innovations faster
One of the biggest semiconductor engineering challenges today is delivering best-in-class devices while dealing with the technology scaling and cost limitations of monolithic IC design…
Tech-Paper
Isolation Device Solution for Intelligent Power Module (IPM) Drive to Realize High-accuracy Industrial Equipment in High Noise Environment
As efforts to protect the environment have advanced, the use of inverters in industrial applications and green energy systems have continued to grow to achieve low-power…
Need Clinical-Grade PPG from Your Wearable? Sometimes It Pays NOT to Shine a Light on a Problem
Heart rate (HR) and blood oxygen saturation (SpO2) are quickly moving from the “desirable” to the “expected” phase in the list of features available in…
More Bang for Your Boost: Driving Heavier Loads with Lower Battery Voltages
Bootstrapping is a technique that can be applied to most boost converters and enables the converter to run down to a lower voltage while still…
How to Design a Good Vibration Sensor Enclosure Using Modal Analysis
A well-constructed mechanical enclosure design for a MEMS accelerometer will ensure that high quality vibration data for CbM is extracted from the monitored asset. The…
Proposed standardization of chiplet models for heterogenous integration
In this paper, the authors, as members of the Chiplet Design Exchange (CDX), propose a set of standardized chiplet models that include thermal, physical, mechanical,…
Five key workflows that deliver 3D IC packaging success
Several factors are converging and driving the chiplet design revolution. This paper explores these factors and outlines five key workflows that address and manage the…
System-level connectivity management and verification of 3D IC heterogeneous assemblies
Capturing the intended system-level connectivity in a multi-substrate 3D IC assembly can be a challenge. This is especially true when each substrate is built using…
Shorten the Time Between P&R and Physical Verification with Calibre PVReady Filler Cell Solution
Using a P&R tool’s built-in fill function to place filler cells during implementation is not only time-consuming, but can create layouts that do not comply…
Parasitic Extraction of MIM/ MOM Capacitor Devices in Analog/RF Designs
The extensive use of MIM/MOM capacitors in analog/RF designs presents parasitic extraction challenges to designers. Understanding best practices and recommended tools for extracting the complex…